1. Field of the Invention
The present invention relates generally to the field of electronics and, more specifically, the present invention relates to phase locked loop circuitry.
2. Background Information
Phase locked loop circuits are a well-known form of circuit useful in synchronizing a clock signal internal to a circuit with an external clock signal. Present day phase locked loop circuits include circuitry to generate an oscillating signal that is phase locked with a reference clock. The oscillating signal is controlled and maintained in response to a control voltage, which is generated and maintained by circuitry of the phase locked loop circuit. Phase locked loop circuits are useful in a variety of electronic applications including synchronizing circuits in computers, communications, etc.
Continuing efforts are being made to reduce power consumption and/or increase battery life in electronic devices such as computers or the like. For example, many present day notebook computers are provided with a standby mode. While in standby mode, circuitry in the notebook computer, including phase locked loop circuitry, is substantially powered down reduce power consumption. Consequently, when active operations are to be resumed on the notebook computer, the circuitry including the phase locked loop circuitry of the computer is powered back up. There is a latency time in the computer during this startup period when the phase locked loop circuitry is powered back up. During this latency time, normal operations are generally unavailable in the computer since circuitry in the computer may not be synchronized properly. Normal operations in the computer may resume after the phase locked loop circuit stabilizes and the control voltage of the phase locked loop circuit is sufficiently charged such that the oscillating signal or a fraction thereof of the phase locked loop circuit is phase locked with the reference clock signal.